Skolkovo School of Synthesis of Digital Circuits


The Skolkovo School of Digital Circuit Synthesis is an initiative designed to rapidly modernize Russian education in digital circuit design at the Register Transfer Level (RTL).
This fundamental technology used by engineers at Apple, Intel, NVidia and other electronic
companies to design chips in smartphones, computers, machine learning accelerators.
For the successful development of such projects in Russia, it is necessary to grow superstar microarchitects who form the backbone of development teams within electronic companies.
It makes sense to start this process from school, in much the same way as the formation of professional mathematicians, winners of sports olympiads and concert musicians takes place.

Partner and sponsor of the project Skolkovo Foundation 

Sponsor of the project  YADRO Microprocessors

Broadcast Sponsor Company Cadence Design Systems.


Skolkovo School of Digital Circuit Synthesis, main course

The program allows you to start from scratch and look inside the development of modern microcircuits.

This is a semester-long program of the three-day school at ChipEXPO, with a volume of material at the level of a university laboratory workshop on reconfigurable FPGA chips, to which elements of computer architecture and processor core microarchitecture courses are added, a demonstration of systolic arrays for hardware acceleration of artificial intelligence calculations, as well as a basic tutorial on using professional ASIC design tools for mass production.

Held in the Skolkovo Technopark for three hours every Saturday on the dates below. Designed for three categories of listeners:

1. High school students of the Olympiad type will be able to understand what work in the microelectronics industry is like: designing chips for smartphones, game consoles and self-driving cars, or using reconfigurable logic chips to control a spacecraft.

2. Junior students will be able to lay a solid foundation for further study of circuitry and computer architecture in their universities.

3. Teachers of universities, physical schools or technology circles will be able to find material for setting up or improving their courses.

The final two sessions are devoted to simulating an interview for a position as a digital circuit designer at the register transfer level. To do this, microarchitectural puzzles are used based on real questions that are asked at interviews in the top 20 electronic and aerospace companies in the world. The winners will receive incentive prizes and recommendations.

Lesson plan:


October     30, 2021: 1. Introduction to the design route and exercises with combinational logic.
November 13, 2021: 2. Architecture: view of the processor from the programmer's point of view.
November 20, 2021: 3. Sequential logic and finite automata.
November 27, 2021: 4. Analysis of the educational project: recognition and generation of sounds and melodies.
December 4,   2021: 5. Pipelines and systolic arrays, with an application for artificial intelligence.
December 11, 2021: 6. Analysis of the educational project: a modular graphic game with sprites.
December 18, 2021: 7. Microarchitecture of a single-cycle processor.
December 25, 2021: 8. Pipeline processor microarchitecture.


*** Section "Introduction to Central Processing Units"

January 15, 2022: 9. Processor cache design and performance measurement.

*** Section "Standard blocks and design techniques"

January 22, 2022: 10. Building blocks and design techniques: FIFO queues and credit counters.
January 29, 2022: 11. Building blocks and design techniques: arbitrators, banks, and memory sharing.

** Section "Mass ASIC design route"

February   5, 2022: 12. Trying the RTL2GDSII route: how mass-produced microcircuits are developed. Part I. Cadence.
February 12, 2022: 13. Trying the RTL2GDSII route: how mass-produced microcircuits are developed. Part II. Synopsys.
February 19, 2022: 14. Physical design route from Siemens EDA/ Mentor Graphics.
February 26, 2022: 15. Advanced debugging with timing diagrams and temporal logic assertions.

*** Section "Continuing to work with peripherals, graphics and sound"

March 5, 2022: 16. Connecting an FPGA board to a computer via the PuTTY text console using a USB-to-UART adapter.
March 12, 2022: 17. Frame buffer graphics.

March 19, 2022: 18. First steps in digital signal processing (DSP) / Digital Signal Processing (DSP). Experiments with digital filter, microphone and amplifier. Changing the timbre of a voice or melody, creating an echo. Presentation on the practical use of the Fourier transform and
demonstrating it on FPGA.

*** Section "Standard blocks and design techniques: continued"

March 26, 2022: 19. Clock Domain Crossing - CDC. Data exchange between blocks that operate at different frequencies.

***Section "Advanced microarchitecture of central processors"

April 2, 2022: 20. Out of order execution of instructions, Tomasulo's algorithm and register renaming.
April 9, 2022: 21. Three educational packages with learning processors:

1. Exercises with the RISC-V architecture YRV training processor from Monte Dalrymple.
2. Exercises with Imagination Technologies' RVfpga package based on Western Digital's RISC-V core, using Xilinx Artix-7 FPGA boards.
3. Using the TIE language to expand Tensilica XTensa processors from Cadence Design Systems.

*** Section "Checking and competition"

April 16, 2022: 22. Simulated interview for the position of a digital circuit designer at the level of register transfers.
April 23, 2022: 23. Analysis of the simulation of interviews and presentations of the projects of the School participants.