Business programm

The event will be held as part of the ChipEXPO-2021 business program.

The organizers of the ChipEXPO-2021 exhibition have started preparing the business program.
More than 15 employees and leading specialists from various companies participate in the training, such as: IVA Tech, Moscow State University, MIPT, HSE MIEM, MIET, Samara University, Chernigov National Technological University (Ukraine), ITMO University, IRO company, Institute for System Programming named after ... V.P. Ivannikov Russian Academy of Sciences, Innopolis University Design Center, NPO Elvis, KM211, Juniper Networks, Inc. (USA),

The key events of the business program will be:
1. Program for senior students and developers (first part of the program) and for junior students and high school students (second part of the program).
2. Seminar: The Art of Functional Verification: You Can't Create a Chip Without It.
2.1 Modern technologies for verification of microcircuits: not only writing tests, but creating an environment that guarantees quality and performance.
2.2 Verification not only for verifiers, part 1:
The use of the temporal logic language SystemVerilog Assertions by the developer of the RTL block to improve quality, control the coverage of special cases and document functionality.
2.3 Verification not only for verifiers, part 2: the use of functional coverage groups in SystemVerilog by the RTL developer to verify the completeness of the test suite, document functionality and improve the quality by means of formal verification.
2.4 What is the Universal UVM Verification Methodology and the limits of its applicability.
2.5 Increasing the productivity of the verifier engineer through the use of portable tests in C / C ++ at all stages of development: from autonomous verification of a block, subsystem, system-on-chip and prototyping to a finished integrated circuit.

3. Seminar: The path to the factory on open design routes.
3.1 Open paths for microcircuit design: an alternative to commercial CAD manufacturers and a chance for Russian algorithm developers.
3.2 Using open design paths Qflow and OpenLANE to measure the physical performance of educational and research projects in microarchitecture.

A detailed description of the event is posted on the exhibition website in the "Business program" section (http://www.chipexpo.ru/programm) and applications for participation in the events of the business program are accepted. The exact schedule with distribution by day and hour will be posted later.
Depending on the epidemiological situation, the business program will be held offline with broadcast on YouTube or online on a dedicated YouTube channel.
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Historical reference:

Verilog HDL (Hardware Description Language) is a textual hardware description language. It is used for design, simulation, verification of digital microcircuits, boards and systems.

The Verilog language was developed in 1984-1985 by Phil Moorby during his time at Gateway Design Automation. At the same time, the first Verilog simulator appeared: Verilog-XL. Gateway was later bought by Cadence Design Systems and made the Verilog HDL public domain in 1990. In IEEE-1364-1995, IEEE Standard Hardware Description Language Based on the Verilog (R) Hardware Description Language.

Later, an "extended" version of the language appeared - SystemVerilog, developed by Accellera (www.accellera.org).

SystemVerilog focuses on project verification, the language contains elements of object-oriented programming.

How to learn to design, model and verify circuits on Verilog?

The main problem of learning this language for people who already know how to program: Verilog requires a different mental model of computation. Not instruction chains, as in classical programming languages, but parallel combinational logic clouds that store states in sequential logic registers.

The sooner the brain gets hooked on Verilog, the better. It's like playing the violin or professional sports - virtuosos and Olympic champions have been doing this since childhood. But how do you make Verilog interesting for the student? Simple exercises with blinking lights on FPGAs / FPGAs quickly get boring, exercises that are more difficult, such as designing processors, require too much investment of attention before getting interesting. Exercises with sensors, such as a light sensor, boil down to constructing a state machine for SPI or I2C protocols on FPGAs and do not show all aspects of circuit design.

After three years of experimenting with schoolchildren in Moscow, Kiev and Novosibirsk, a universal way was found for a quick and interesting introduction of a student to Verilog by designing video games in hardware. This example teaches best the concepts of concurrency, modular hierarchy, designing a small pipelined data path, and writing a state machine for a game scenario. The basic version can be flexibly changed by creating.

The author and enthusiast of carrying out such experiments was Yuri Panchul, currently the Staff ASIC RTL Design Engineer at Juniper Networks (USA), but in general a cool specialist in microcircuit technologies. He regularly comes to Russia and conducts Verilog design schools in Zelenograd with exercises on FPGA reconfigurable logic boards. We contacted Yuri and offered to jointly organize and conduct a three-day digital design school at Verilog during the ChipEXPO-2020 exhibition in Skolkovo (September 15-17). High school students (from the 9th grade and above) and, if they want, junior students can participate in this project. Schoolchildren up to 9th grade, as a rule, do not sufficiently perceive sequential logic, although we are ready to try with younger students if they take the exercises of the online course created by Yuri together with RUSNANO. MIET, HSE MIEM, ITMO, MIPT, a number of universities and companies were invited to implement the project, and as assistants - students, postgraduates and students of physics and mathematics schools who have already taken part in Zelenograd schools.

We plan to write instructions in advance for everyone who will teach and assist in their conduct. We plan, first of all, to attract students of physics and mathematics schools and winners of Olympiads, but we are ready to accept any schoolchildren and junior students who will take three parts of a theoretical course from RUSNANO before practical exercises in Skolkovo, under the general title "How the creators of smart nanochips work": "From a transistor to a microcircuit", "The logical side of digital circuitry", "The physical side of digital circuitry". This course is necessary for the participants to understand what they are doing, since the time for the practical course at the event is limited, and this kind of information does not immediately fit into the head. Upon presentation of the certificate of completion of the online course, we, the organizers of the event, will be ready to distribute a limited number of FPGA boards for free, with which participants can work at home, before, during and after the event in Skolkovo. For everyone else who wants to take a course at the "School ...." we will post information about where you can buy boards yourself

If we talk about the degree of computer skills, then this is not so important, since everything will be shown in the integrated Intel FPGA / Altera Quartus environment under Linux or Windows. Of course, if someone knows how to program (for example, in python), then this is a plus, but not a prerequisite. We plan to make a three-day school for one team, say 20-40 people - or more if there are many assistants. In parallel with this, we can do overview lectures every day for a wide audience of online visitors - up to 200 people, if so many. The experience of such lectures has been confirmed at Innopolis University - see Part 1 and Part 2

 
If you do not want (or cannot) become a member of the "School", you can simply attend lectures and workshops.
 

 

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