Skolkovo School of Synthesis of Digital Circuits on Verilog

Skolkovo school of synthesis of digital circuits on Verilog

The organizer of the ChipEXPO - 2020 exhibition (September 15 - 17, 2020, Skolkovo Innovation Center, Technopark) invites junior students and senior schoolchildren to get acquainted with three technologies that made our world of smartphones, fast Internet and unmanned vehicles possible.
These are digital chip design technologies: Verilog hardware description language, logic synthesis, and reconfigurable FPGA chips.
They originated in the 1980s, increased the productivity of engineers by two orders of magnitude, and also allowed prototyping chips without making them in a factory.
These technologies are now used by everyone: both American Apple, NVidia, Tesla, and Russian companies ELVIS and NIISI, which design processors for spacecraft.
and cameras for face recognition.
Digital synthesis technologies make it possible to create very complex devices, but their basic principles are quite accessible to the advanced student.
Due to the coronavirus, the seminar will be held online, as part of the business program of the ChipEXPO-online exhibition, so not only Moscow schoolchildren, but also schoolchildren from all over Russia, Ukraine, Kazakhstan, California and other countries and regions will be able to take part in it.

Historical reference:
Verilog HDL (Hardware Description Language) is a textual hardware description language. It is used for design, simulation, verification of digital microcircuits, boards and systems.
The Verilog language was developed in 1984-1985 by Phil Moorby during his time at Gateway Design Automation. Then the first Verilog simulator appeared: Verilog-XL. Gateway was later acquired by Cadence Design Systems and made the Verilog HDL public domain in 1990. In 1995, the language became the IEEE-1364-1995 standard, IEEE Standard Hardware Description Language Based on the Verilog (R) Hardware Description Language.
Later, an "extended" version of the language appeared - this is SystemVerilog, developed by
Accellera (
SystemVerilog focuses on project verification, the language contains elements
object oriented programming.

How to learn to design, model and verify circuits on Verilog?
The main problem of learning this language for people who already know how to program: Verilog requires a different mental model of computation. Not instruction chains, as in classical programming languages, but parallel combinational logic clouds that store states in sequential logic registers.
The sooner the brain gets hooked on Verilog, the better. It's like playing the violin or professional sports - virtuosos and Olympic champions have been doing this since childhood.

But how do you make Verilog interesting for the student? Simple exercises with blinking lights on FPGAs / FPGAs quickly get boring, exercises that are more difficult, such as designing processors, require too much investment of attention before getting interesting.
Exercises with sensors, such as a light sensor, boil down to constructing a state machine for SPI or I2C protocols on FPGAs and do not show all aspects of circuit design.
After three years of experimenting with schoolchildren in Moscow, Kiev and Novosibirsk, it was found
a universal way for a quick and interesting introduction of a student to Verilog by designing video games in hardware. This example best teaches you the concepts of concurrency, modular hierarchy, designing a small pipelined data path, and writing a state machine for your game scenario.
The basic version can be flexibly changed by creating new games.

The author and enthusiast of such experiments was Yuri Panchul, currently the Staff ASIC RTL Design Engineer at Juniper Networks (USA), but in general a cool specialist in microcircuit technology.
He regularly comes to Russia and conducts Verilog design schools in Zelenograd with exercises on FPGA reconfigurable logic boards.
We contacted Yuri and offered to jointly organize and conduct a three-day digital design school at Verilog during the ChipEXPO-2020 exhibition in Skolkovo (September 15-17).
High school students (from the 9th and above) and, if they want, junior students can participate in this project. Schoolchildren up to 9th grade, as a rule, do not sufficiently perceive sequential logic, although we are ready to try with younger students if they take the exercises of the online course created by Yuri together with RUSNANO.
MIET, HSE MIEM and ITMO were invited to implement the project, and as assistants - students and postgraduates, as well as students of physics and mathematics schools that have already taken part in Zelenograd schools.
We plan to write instructions in advance for everyone who will teach and assist in their conduct.

We plan, first of all, to attract students of physics and mathematics schools and Olympiad winners, but we are ready to accept any schoolchildren and junior students who will take three parts of a theoretical course from RUSNANO before practical exercises in Skolkovo, under the general title "How the creators work
smart nanochips ":" From transistor to microcircuit "," The logical side of digital circuitry "," The physical side of digital circuitry ".

This course is essential for the participants to understand what they are doing, as the time for the workshop is limited and information of this kind does not immediately fit into the head.
Upon presentation of the certificate of completion of the online course, we, the organizers of the seminar, will be ready to distribute a limited number of FPGA boards with which participants can work at home, before, during and after the seminar in Skolkovo.

Seminar in three parts:

1. Elementary exercises with combinational and sequential logic, such as displaying an inscription on a dynamic seven-segment indicator using a shift register control.

2. Creation of a video game with sprites, with output from FPGA to VGA monitor.

3. Construction of the simplest processor, based on the schoolRISCV project, adaptation of the schoolMIPS processor, described in the recently published textbook "Digital synthesis" in DMK-Press.

If we talk about the degree of computer proficiency, then this is not so important, since everything will be shown in the integrated Intel FPGA / Altera Quartus environment under Linux or Windows.
Of course, if someone knows how to program (for example, in python), then this is a plus, but not a prerequisite.
We are planning to do a three-day school for one team, say 20 people - or more if there are many assistants.
In parallel with this, we can do overview lectures for a wide audience every day -
up to 200 people, if so many.
The experience of such lectures has been confirmed at Innopolis University - see Part 1 and Part 2.